The Setup window’s Sampling tab defines how the GoLogic acquires data. The sampling setup should be defined first because it determines which channels are available to capture data. Some sampling modes require specific channel connections.

Normal timing
The GoLogic samples the channel inputs at a fixed frequency which you select. For example, 500 million samples per second are stored to memory when 500 MHz normal timing is used. To capture a valid representation of the input signals, they must be 4 to 10 times slower than the GoLogic's sampling rate. In other words, the GoLogic must over-sample the input signals by 4X to 10X. The greater the over-sampling ratio, the more accurate the captured data represents the actual input signals. The four special clock channels capture data just like the normal channels when timing analysis is active. When state modes are used, data is not captured on the special clock channels.	Normal timing
Transitional timing
Like normal timing, the GoLogic over-samples the channel inputs at a fixed frequency you select. However, transitional timing only stores a sample when at least one input signal changes. This eliminates redundant samples from the trace and uses the GoLogic memory depth more efficiently. Transitional timing A timestamp value is recorded when each sample is stored to memory and allows each sample’s elapsed time to be determined. Half of the GoLogic's memory is used to store the timestamp values, so the maximum number of samples which can be stored is halved. However, the effective memory depth actually increases because no redundant samples are stored and the time-span of the overall trace is much longer. Choosing which channels can detect input signal changes is a powerful feature of transitional timing. Chapter 3 - Setup step two: channels describes how to specify which channels detect transitions.
4-channel transitional timing
4-channel transitional timing is tailored especially for serial bus analysis where few channels but large memory depth is required. This mode is identical to standard transitional timing analysis except only channels CA0, CA1, CA2, and CA3 are available for capture. By disabling all other channels, the GoLogic can quadruple its transitional timing memory depth, which is twice the normal timing memory depth. 4-channel transitional
Simple state
Rather than over-sample the data, the CA0 "clock" channel is connected to the test circuit’s clock signal. The input signal connected to CA0 drives the GoLogic sampling and samples the data inputs synchronously with the test circuit. The data can be sampled on the rising edge, falling edge, or any edge of the CA0 clock channel. However, only the GoLogic-72 models support the "any edge" clock source. The GoLogic supports state frequencies up to 125 MHz. However, the source clock signal cannot exceed 62.5 MHz when Both Edges is selected (which is an effective 125 MHz clock). The GoLogic cannot determine the source clock signal's frequency. Therefore, you must enter the source clock’s frequency so the GoLogic software can display each sample’s elapsed time correctly. If no frequency is provided, the software assumes a 125 MHz external clock rate. The CA1, CA2, and CA3 clock channels can be used as data inputs when simple state analysis is used.	Simple state
Simple state with timestamp
Simple state with time stamp is useful when the clock source is not constant or when selective storage is used and you need to know how frequently the data is stored. This mode is identical to simple state except a timestamp value is stored with each sample so that the elapsed time of each sample is known. State with timestamp Like transitional timing, half the memory depth is used to store the timestamp values. Therefore, the maximum memory depth is half what simple state can capture. If selective storage is not used and the source clock is constant, then use simple state mode to capture more samples.
Simple state (multiple clocks)
Up to four clock channels can be used to determine when the GoLogic samples the data inputs. A clock equation described below defines how several clock signals are combined to define the GoLogic's sample rate. Simple state with multiple clocks The CA0, CA1, CA2, and CA3 clock channels are disabled when this sampling mode is active. Trace values cannot be captured on the clock channels. The normal channel inputs must be used to capture the input signals.
The clock equation rules
The clock equation must have at least one edge. Rising and falling clock operands are grouped together. High and low clock operands are grouped together. Inside each group, clock operands are combined first using an OR operator. Edge-groups and level-groups are combined last with an AND operator...
(Rising S1 OR Falling LRE*) AND (Low S0 OR High S2)
Complex state
Complex state is identical to simple state with multiple clocks except that two clock equations are used. The two clock equations combine signals output at different moments into a single GoLogic trace sample. The combined samples are easier to analyze and use the GoLogic memory depth more efficiently. Complex state The CA0, CA1, CA2, and CA3 clock channels are disabled when this sampling mode is active. Trace values cannot be captured on the clock channels. The normal channel inputs must be used to capture the input signals.
Dual clock equations rules
The GoLogic temporarily holds the first phase signals when the slave clock equation occurs. The second phase signals are combined with the first phase and stored to memory when the master clock equation occurs. Each clock equation obeys the same clock equation rules described in the simple state section. Four complex state options are available which define which channels are used to capture and how the GoLogic combines the first and second phases. These state options are...
16-bit multiplex on pod A
Use this option if 16 or fewer signals sharing 8 or fewer pins must be combined into one sample. For example, an 8051 microprocessor's address and data bus can be de-multiplexed with this mode. Connect channels A00 through A07 to the shared signals. Channels A08 through A15 are left unconnected. When the slave equation occurs, the data on channels A00 through A07 is internally shifted to channels A08 through A15 and held temporarily. When the master equation occurs, the data stored in the first phase is combined with the new data on channels A00 through A07 and the resulting logic analyzer sample is stored to memory...
The signals connected to channels B00 and above are also stored with the master equation.
48-bit multiplex on pods A, B, C
Use this option if 48 or fewer signals sharing 24 or fewer pins must be combined into one sample. For example, the Z80 and Z180 microprocessor's address and data bus can be de-multiplexed with this mode. Connect channels A00 to A07, B00 to B07, and C00 to C07 to the shared signals. Channels A08 to A15, B08 to B15, and C08 to C15 are left unconnected. When the Slave equation is valid, the data on channels A00 to A07, B00 to B07, and C00 to C07 is internally shifted to channels A08 to A15, B08 to B15, and C08 to C15 and held temporarily. When the Master equation is valid, the data stored during the initial phase is combined with the new data on channels...
The signals connected to channels D00 and above are also stored with the master clock equation.
16-bit non-multiplex on pod A
Use this option if 16 or fewer signals that do not share pins are output at different times and must be combined into one sample. Connect channels A00 through A15 to the signals output in the initial phase. Connect channels B00 through D15 to the signals output in the final phase. When the Slave clock equation is valid, the data on channels A00 through A15 is held temporarily. When the Master clock equation is valid, the data from the initial phase is combined with the new data from channels B00 through D15 and the resulting logic analyzer sample is stored...
32-bit non-multiplex on pods A, B
Use this option if 32 or fewer signals that do not share pins are output at different times and must be combined into one sample. Connect channels A00 through B15 to the signals output in the initial phase. Connect channels C00 through D15 to the signals output in the final phase. When the Slave clock equation is valid, the data on channels A00 through B15 is held temporarily. When the Master clock equation is valid, the data from the initial phase is combined with the new data from channels C00 through D15 and the resulting logic analyzer sample is stored...
Memory depth
This value is common to all sampling modes and defines the total number of samples captured the next time the GoLogic runs. The minimum capture size for is eight thousand samples (8K), but fewer samples may be captured if the GoLogic is stopped manually or the incoming samples become inactive while using transitional timing or any state modes. The maximum capture size depends on the GoLogic model and the active sampling mode.
Double memory depth
By halving the channels, the GoLogic can reorganize how its memory is used to capture twice as many samples. However, the double-depth option is only listed when the GoLogic model and the sampling mode allow it... The “(A & B only)” note indicates that the GoLogic operates in 36-channel mode when this memory depth is selected. This option allows a 1M GoLogic-72 to capture 2M samples across 36 channels. Likewise, a 2M GoLogic-72 can capture 4M samples across 36 channels. Note: The GoLogic-36 does not support the double-depth feature.

The Serial Bus Definition Area is displayed when any serial bus capture mode is active...

• Total serial buses: Up to 32 serial buses can be captured and displayed together. Selecting "0" disables the serial bus tools.
• Re-convert open data: Since the serial conversion process requires significant CPU time, the raw serial data is converted to parallel form only when new trace data is captured or a project file is opened. The "Re-convert" button allows you to adjust the serial bus definitions and then re-convert the data. This is a very handy feature when you aren't certain of the bus parameters. We recommend capturing a small trace of 8K samples while experimenting so the conversion process is fast as possible.
• Type: Choose the serial bus type. Notice that different serial bus types can be captured and displayed together at the same time.
• Name: Enter a meaningful name for each serial bus if two or more buses are defined. This name identifies the bus in the WaveForm window and the Serial Display plugin. If only one bus is captured, the default name can be used.
• Data: Choose the source data to convert. Reference data can be loaded from a project file and converted to parallel form by choosing the "Reference" option. Otherwise, choose the "Trace" option to analyze new trace captures.

The remaining serial bus options are specific to each bus type. These options are described below with each bus type.

Once all serial buses are defined, you may switch back to Transitional Timing mode and use the  TriggerForms to trigger on a non-serial signal while analyzing serial buses. Normal Timing mode can also be used to capture raw serial bus data, but the GoLogic memory depth will fill much quicker and provide a must smaller time-window of bus activity.

The following Serial Bus Definitions are specific to the I2C bus...

• Trigger bus: When I2C timing or state mode is active, the I2C bus connected to CA0 and CA1 is always used for triggering. This is a hardware limitation inside the GoLogic when I2C timing or state mode is used. Therefore, this option is a reminder of which channels can trigger the GoLogic.
• Speed: The GoLogic supports I2C bus speeds from 100 MB/s to 3.4 MB/s.
• SCL: Choose the channel connected to the I2C clock signal.
• SDA: Choose the channel connected to the I2C data signal.

• Trigger bus: Any SPI bus connected to any channels can be used for triggering. However, only one bus can be used for triggering.
• Mode: Choose the SPI bus mode. See the "SPI Mode" topic below for details.
• Width: Enter the number of bits in each bus value. Packet widths from 2 to 64 bits are supported.
• CLK period: Measure the time between two adjacent rising edges on the CLK signal and enter this value. Entering a valid period allows the conversion software to ignore glitches and runt-pulses in the data.
• CLK: Choose the channel connected to the SPI clock signal. The software automatically creates a channel group for this signal in the "Step 2: Channels" tab. A line in the WaveForm window is also automatically inserted to display both the raw clock signal and the converted SPI bus.
• MISO: Choose the channel connected to the SPI "Master In Slave Out" signal.
• MOSI: Choose the channel connected to the SPI "Master Out Slave In" signal.
• Bit-order: Choose the order the serial bits are used in the converted parallel values.
• Invert data: Check this option to bit-wise invert the bus values.

Motorola's documentation on the SPI bus is required reading before using the GoLogic's SPI analysis features. SPI bus operation can vary between implementations, and you must know exactly how your SPI bus operates.

CPHAS is the clock "phase" value. CPOL is the clock "polarity" value. These values define how the serial SPI bits are latched. Motorola defines the four SPI bus modes as follows…

The following timing diagram illustrates the SPI bus modes…

SPI has no official IEEE standards and each implementation can differ. Specifically, the SS* signal can be used as either a "frame" or a "chip select" mechanism. Therefore, the GoLogic software does NOT use the SS* signal to analyze the bus. Of course, you can connect a spare channel and capture the SS* signal if needed.

The following Serial Bus Definitions are specific to the UART bus...

• Baud: Select (or enter) the bits-per-second used for the UART bus. You can choose from the common baud rates listed or enter a custom baud in the control's edit area. Fractional baud rates are supported.
• Logic: Select the logic-type used for the raw signals. If you are connected to the raw, inverted-logic +/-12V UART signal, then choose the "Raw" logic option. If you are connected to the processed, TTL logic on a UART chip, then choose the "TTL" option. Whenever possible, we recommend capturing from a UART chip. The UART provides cleaner signals which the GoLogic software will interpret more reliably.
• Chan: Choose the channel connected to the UART signal. The software automatically creates a channel group for this signal in the "Step 2: Channels" tab. A line in the WaveForm window is also automatically inserted to display both the raw signal and the converted UART bus.
• Bit-order: Choose the order the serial bits are used in the converted parallel values. The bits can arrive Least Significant Bit first (LSB) or Most Significant Bit first (MSB).
• Width: Enter the number of bits in each bus data value. Packet widths from 2 to 64 bits are supported.
• Parity: Choose the type of parity bit used in each packet.
• Stop-bits: Choose the number of stop-bits in each packet.
• Invert data: Check this option to bit-wise invert the bus values.

The following Serial Bus Definitions are specific to the CAN bus...

• Baud: Select (or enter) the bits-per-second used for the CAN bus. You can choose from the common baud rates listed or enter a custom baud in the control's edit area. Fractional baud rates are supported.
• Logic: Select the logic-type used for the raw signals. The CAN physical layer is not defined by the Bosch® specification. If your raw signals use inverted-logic, then choose the "Inverted" logic option. If your raw signals use positive-logic , then choose the "Normal" option.
• Chan: Choose the channel connected to the CAN signal. The software automatically creates a channel group for this signal in the "Step 2: Channels" tab. A line in the WaveForm window is also automatically inserted to display both the raw signal and the converted CAN bus.

The following Serial Bus Definitions are specific to the LIN bus...

• Baud: Select (or enter) the bits-per-second used for the LIN bus. You can choose from the common baud rates listed or enter a custom baud in the control's edit area. Fractional baud rates are supported
• Version: Choose the LIN bus version.
• Logic: Select the logic-type used for the raw signals. If your raw signals use inverted LIN logic, then choose the "Inverted" logic option. If your raw signals use normal LIN logic , then choose the "Normal" option.
• Chan: Choose the channel connected to the LIN signal. The software automatically creates a channel group for this signal in the "Step 2: Channels" tab. A line in the WaveForm window is also automatically inserted to display both the raw signal and the converted LIN bus.

The following Serial Bus Definitions are specific to the Bitstream bus...

• Logic: Select the logic-type used for the raw signals. The inverted logic option inverts the data bits.
• Clk period: Enter the time which describes the clock period. If the clock signal does not to have a 50% duty cycle, just enter double the elapsed time for a valid pulse. A precise value isn't important. Entering a valid period allows the conversion software to ignore glitches and runt-pulses in the data.
• Clk edge: Choose the clock edge where the data bits should be latched: rising. falling, or both edges.
• CLK: Choose the channel connected to the clock signal. The software automatically creates a channel group for this signal in the "Step 2: Channels" tab. A line in the WaveForm window is also automatically inserted to display both the raw signal and the converted bitstream bus.
• Data: Choose the channel connected to the data signal. The software automatically creates a channel group for this signal in the "Step 2: Channels" tab. A line in the WaveForm window is also automatically inserted to display both the raw signal and the converted bitstream bus.
• Width: Enter the number of bits in each bus data value. Packet widths from 2 to 64 bits are supported.
• Start at...: Define the trace data position where the bitstream conversion starts each time the "re-convert data" button is clicked. Except when the "first sample" or "trigger" options are used, the raw bitstream data is not automatically converted each time a new trace is captured. When any moveable data marker is used as the start position, you must first place the marker on the data then click the "re-convert data" button.