- Number of channels - 72 or 36 depending on
model.
- Memory depth (72 channel models) - 1M
version: 1,048,576 samples across all channels. Double-depth option
increases the depth to 2,097,152 samples. Transitional timing and state
analysis with time stamp halve the memory depth to 524,288 samples. 2M
version: 2,097,152 samples across all channels. Double-depth option
increases the depth to 4,194,304samples. Transitional timing and state
analysis with time stamp halve the memory depth to 1,048,576 samples.
- Memory depth (36 channel models) - 2M
version: 2,097,152 samples per channel. Transitional timing and state
analysis with time stamp halve the memory depth to 1,048,576 samples.
Double-depth option not available. 4M version: 4,194,304 samples per
channel. Transitional timing and state analysis with time stamp halve the
memory depth to 2,097,152 samples. Double-depth option not available.
- Probe inputs - 240 Kohm input impedance
shunted by 10 picofarads. 1 nanosecond maximum skew between channels 2
nanosecond setup time with 0 nanosecond hold time.
- Threshold levels - One independent
threshold level per 16 channels. Variable between -4.90 volts and +5.27
volts in about 40 millivolt increments. Voltage swings as low as 600
millivolts are supported.
- Minimum input voltage range - 0.6 volt
peak to peak around the threshold voltage. Minimum high level is 0.3 volt
above threshold voltage. Minimum low level is 0.3 volt below threshold
voltage.
- Clock channels - 4 clock channels are
available when using state analysis.
- Minimum sampling rate - 500 Hz timing
analysis. No minimum rate for state analysis.
- Maximum sampling rate - 500 MHz timing
analysis. 125 MHz with state analysis. Actual maximum state analysis
sampling rate is determined by the source clock’s signal quality.
- Time stamp resolution - See the Time stamp
resolution appendix for a table of time stamp resolutions for each clock
mode.
- Maximum time between samples - See Time
stamp resolution appendix for a table of maximum time stamp values for
each clock mode.
- Total time in data - See Time stamp
resolution appendix for a table of the maximum time in the data for each
clock mode.
- Trigger patterns - 8 normal trigger
patterns plus 2 edge events (timing analysis) or 2 range events (state
analysis).
- Sequence levels - 8 sequence levels. 2
patterns + 2 edge/range per sequence level.
- Sequence counter - One 20-bit counter per
sequence level. Minimum counter value is 2 and maximum is 1,046,575.
- Sequence timer - See Global timer limits
and Level timer limits appendices for a table of the minimum and maximum
timer values for each sampling rate.
- Trigger-out signal - The trigger-out
signal uses TTL logic. The connector outputs an active low signal. The
signal goes low when the logic analyzer triggers.
- Dimensions - Width: 3.8" (9.5 cm); Length:
6.3" (16 cm); Height: 1.2" (3 cm); Weight: 14 oz. (410 grams) not
including cable, lead sets, etc.
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